(Not Applicable)
(Not Applicable)
The present invention relates generally to chip stacks, and more particularly to a chip stack having connections routed from the bottom to the perimeter thereof to allow multiple integrated circuit chips such as BGA devices to be quickly, easily and inexpensively vertically interconnected in a volumetrically efficient manner.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant""s U.S. Pat. Nos. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a volumetrically efficient chip stack. In the chip stack of the present invention, connections are routed from the bottom of the chip stack to the perimeter thereof so that interconnections can be made vertically which allows multiple integrated circuit chips such as BGA, CSP, fine pitch BGA, or flip chip devices to be stacked in a manner providing the potential for significant increases in the production rate of the chip stack and resultant reductions in the cost thereof.
In accordance with the present invention, there is provided a chip stack comprising at least two base layers (i.e., an upper base.layer and a lower base layer). Each of the base layers includes a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the upper and lower base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. In addition to the base layers and interconnect frame, the chip stack comprises at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. The integrated circuit chip electrically connected to the first conductive pattern of the lower base layer is at least partially circumvented by the interconnect frame and at least partially covered by the upper base layer. The chip stack further preferably comprises a transposer layer which includes a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of the lower base layer is electrically connected to the third conductive pattern of the transposer layer.
In the present chip stack, the base substrate of each of the base layers defines opposed, generally planar top and bottom surfaces. The first conductive pattern itself comprises first and second sets of base pads which are disposed on the top surface of the base substrate, with the base pads of the second set being electrically connected to respective ones of the base pads of the first set via conductive traces. In addition to the first and second sets of base pads, the first conductive pattern includes a third set of base pads disposed on the bottom surface of the base substrate and electrically connected to respective ones of the base pads of the second set. More particularly, each of the base pads of the second set is preferably electrically connected to a respective one of the base pads of the third set via a base feed-through hole. The base feed-through hole is preferably plugged with a conductive material selected from the group consisting of nickel, gold, tin, silver epoxy, and combinations thereof. The integrated circuit chips are disposed upon respective ones of the top surfaces of the base substrates and electrically connected to at least some of the base pads of respective ones of the first sets. Additionally, the base pads of the second set of the lower base layer are electrically connected to the second conductive pattern of the interconnect frame, as are the base pads of the third set of the upper base layer.
The interconnect frame of the chip stack itself defines opposed, generally planar top and bottom surfaces, with the second conductive pattern comprising first and second sets of frame pads disposed on respective ones of the top and bottom surfaces. Each of the frame pads of the first set is electrically connected to a respective one of the frame pads of the second set via a frame feed-through hole which is also plugged with a conductive material preferably selected from the group consisting of nickel, gold, tin, silver epoxy, and combinations thereof. The interconnect frame is preferably disposed between the upper and lower base layers such that the frame pads of the second set are electrically connected to respective ones of the base pads of the second set of the lower base layer, with the frame pads of the first set being electrically connected to respective ones of the base pads of the third set of the upper base layer.
The transposer substrate of the present chip stack also defines opposed, generally planar top and bottom surfaces, with the third conductive pattern comprising first and second sets of transposer pads disposed on respective ones of the top and bottom surface of the transposer substrate. The transposer pads of the first set are electrically connected to respective ones of the transposer pads of the second set. Additionally, the base pads of the third set of the lower base layer are electrically connected to respective ones of the transposer pads of the first set.
In the present chip stack, the transposer pads of the first set, the frame pads of the first and second sets, and the base pads of the second and third sets are preferably arranged identical patterns. Additionally, the transposer and base substrates each preferably have a generally rectangular configuration defining opposed pairs of longitudinal and lateral peripheral edge segments. The interconnect frame itself preferably has a generally rectangular configuration defining opposed pairs of longitudinal and lateral side sections. The transposer pads of the first set extend along the longitudinal and lateral peripheral edge segments of the transposer substrate. Similarly, the first and second sets of frame pads extend along the longitudinal and lateral side sections of the interconnect frame, with the second and third sets of base pads extending along the longitudinal and lateral peripheral edge segments of the base substrate. Each of the transposer pads of the second set preferably has a generally spherical configuration, with each of the transposer pads of the first set and each of the frame pads of the first and second sets preferably having a generally semi-spherical configuration.
Each of the integrated circuit chips of the present chip stack preferably comprises a body having opposed, generally planar top and bottom surfaces, and a plurality of conductive contacts disposed on the bottom surface of the body. The conductive contacts of each of the integrated circuit chips are electrically connected to respective ones of the base pads of the first set of a respective one of the first conductive patterns. The transposer pads of the second set, the base pads of the first set, and the conductive contacts are themselves preferably arranged in identical patterns. The chip stack further preferably comprises a layer of flux/underfill (also referred to as a xe2x80x9cno flow-fluxing underfillxe2x80x9d) disposed between the bottom surface of the body of each of the integrated circuit chips and respective ones of the top surfaces of the base substrates. Each layer of flux/underfill is preferably spread over the base pads of the first set of a respective one of the first conductive patterns. The body of each of the integrated circuit chips and the interconnect frame are preferably sized relative to each other such that the top surface of the body of the integrated circuit chip electrically connected to the lower base panel and at least partially circumvented by the interconnect frame does not protrude beyond the top surface thereof. The integrated circuit chips are preferably selected from the group consisting of a BGA device, a fine pitch BGA device, a CSP device, and a flip chip device. Further, the transposer and base substrates are each preferably fabricated from a polyamide or other suitable circuit board material which may be as thin as about 0.010 inches.
Those of ordinary skill in the art will recognize that a chip stack of the present invention may be assembled to include more than two base layers, more than one interconnect frame, and more than two integrated circuit chips. In this respect, a multiplicity of additional interconnect frames, base layers, and integrated circuit chips may be included in the chip stack, with the second conductive pattern of each of the interconnect frames being electrically connected to the first conductive patterns of any adjacent pair of base layers, and each of the integrated circuit chips being electrically connected to the first conductive pattern of a respective one of the base layers.
Further in accordance with the present invention, there is provided a method of assembling a chip stack. The method comprises the initial step of electrically connecting an integrated circuit chip to a first conductive pattern of a base layer. Thereafter, a second conductive pattern of an interconnect frame is electrically connected to the first conductive pattern such that the interconnect frame at least partially circumvents the integrated circuit chip. Another integrated circuit chip is then electrically connected to the first conductive pattern of another base layer. The first conductive pattern of one of the base layers is then electrically connected to the second conductive pattern of the interconnect frame such that one of the integrated circuit chips is disposed between the base layers. The method may further comprise the step of electrically connecting the first conductive pattern of one of the base layers to a third conductive pattern of a transposer layer. In the present assembly method, a layer of flux/underfill is preferably applied to (i.e., spread over) each of the base layers over portions of the first conductive patterns prior to the electrical connection of respective ones of the integrated circuit chips thereto. All of the electrical connections in the present assembly method are preferably accomplished via soldering.
Still further in accordance with the present invention, there is provided a method of assembling a chip stack which comprises the initial steps of providing a transposer panel, at least two base panels, and at least one frame panel which each have opposed surfaces and a plurality of conductive pads disposed on the opposed surfaces thereof. A plurality of integrated circuit chips are also provided which each have opposed sides and include conductive contacts disposed on one of the sides thereof. In this assembly method, integrated circuit chips are placed upon each of the base panels such that the conductive contacts of each of the integrated circuit chips are disposed on at least some of the conductive pads of respective ones of the base panels. Thereafter, one of the base panels is stacked upon the transposer panel such that at least some of the conductive pads of the base panel are disposed on at least some of the conductive pads of the transposer panel. The frame panel is then stacked upon the base panel such that at least some of the conductive pads of the frame panel are disposed on at least some of the conductive pads of the base panel. Another base panel is then stacked upon the frame panel such that at least some of the conductive pads of the base panel are disposed on at least some of the conductive of the frame panel.
The assembly method further comprises bonding the conductive contacts of the integrated circuit chips to at least some of the conductive pads of the base panel upon which the integrated circuit chips are positioned, bonding at least some of the conductive pads of one of the base panels to at least some of the conductive pads of the transposer panel, and bonding at least some of the conductive pads of the frame panel to at least some of the conductive pads of each of the base panels. The assembly method may further comprise the steps of stacking spacer sheets between one of the base panels and the transposer panel, and between the frame panel and each of the base panels. The spacer sheets each have opposed surfaces and a plurality of openings disposed therein. When stacked between the base and transposer panels and between the frame and base panels, the openings of the spacer sheets are aligned with the conductive pads of such panels.